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CXA2066S
Preamplifier for High Resolution Computer Display
Description The CXA2066S is a bipolar IC developed for high resolution computer displays. Features * Built-in wide band amplifier: 140MHz @ -3dB (Typ.) * Input dynamic range: 1.0Vp-p (Typ.) * High gain preamplifier (17dB) * R, G, and B incorporated in a single package * I2C bus control Contrast control Subcontrast control Brightness control OSD contrast control Cutoff control 4-channel DAC output 2 blanking level modes (0.5V fixed and Pedestal -0.6V) ABL control pin * Built-in sync separator for Sync on Green * Built-in blanking mixing function * Built-in OSD mixing function * Video period detection function * Built-in sharpness function * Built-in VBLK synchronous DAC refresh system Applications High resolution computer displays Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25C, GND = 0V) 14 V * Supply voltage VCC VCC2 7 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 2.05 W Recommended Operating Conditions 12 0.5 Supply voltage VCC VCC2 5 0.5 30 pin SDIP (Plastic)
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98210-PS
CXA2066S
Block Diagram
SDA
1 I BUS DECORDER
2C
D/A CONVERTER CONTRAST SUB CONTRAST (R) SUB CONTRAST (G) SUB CONTRAST (B) CUTOFF (R) OSD GAIN (R) CUTOFF (G) OSD GAIN (G) CUTOFF (B) OSD GAIN (B) CUTOFF (RGB) BRIGHTNESS (RGB) LPF
30 CSYNC
SCL
2 To each MODE switch
29 ABL
COF R
3
28 S/H-R
COF G
4
Rch SUB CONTRAST CONTRAST GAIN CONTROL DATA BLANKING MODE
27 ROUT
COF B
5
26 GND-R BRIGHTNESS 25 S/H-G
COF RGB
6
GAIN CONTROL AMP
RIN
7
OSD GAIN (R)
OSD YS GENERATOR
BLANKING BUFFER BLANKING PULSE AMP OSD SW OSD PULSE (13PIN) YS PULSE (17PIN)
24 GOUT
VCC2
8
5V
VDET, SYNC SEP, SHARPNESS
23 GND-G
SHARPNESS GIN 9 GAIN CONT. T SW SYNC IN 10 VDET COMPARATOR BIN 11 Gch CLP 12 Same as R channel 19 GND-B 20 BOUT 12V 22 VCC
SYNC SEPARATOR
21 S/H-B
OSD-R 13 to OSDSW OSD-G 14 to OSDSW OSD-B 15 to OSDSW Bch Same as R channel
18 BLKING
17 YS to OSDSW 16 VDET
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CXA2066S
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC
Description
1
SDA
1 4k
I2C bus standard SDA (serial data) input/output. VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V
VCC
2
SCL
2 4k 10k
I2C bus standard SCL (serial clock) input. VILMAX = 1.5V VIHMIN = 3.5V
VCC 100
VCC
3 4 5 6
VCC
COF R COF G COF B COF RGB
3 4 5 6
Cut-off adjustment DAC outputs. The output DC is 1 to 4V.
VCC 1k VCC
VCC 14k
VCC 8k VCC
VCC
7 9 11
RIN GIN BIN
1.7V (when clamped)
300 7 9 11 1k
RGB signal inputs. Input via the capacitor.
8
VCC2
5V
5V power supply.
-3-
CXA2066S
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC 100
VCC
VCC
10
SYNC IN
2.8V
10
150
Sync on Green signal input. Input via the capacitor.
VCC
VCC 10k 10k
12
CLP
12
10k
Clamp pulse (positive polarity) input. VILMAX = 0.8V VIHMIN = 2.8V
VCC
13 14 15
OSD-R OSD-G OSD-B
VCC 5k 10k 13 14 15
OSD control inputs. VILMAX = 0.8V VIHMIN = 2.8V
VCC2 VCC2 VCC2 20k 100 5k
VCC2
16
VDET
16
Video detector output. Typ.; High = 4.3V Low = 0.2V
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CXA2066S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC
Description
VCC 5k
17
YS
17
10k
YS (OSD_BLK) input. VILMAX = 0.8V VIHMIN = 2.8V
VCC VCC 4k
VCC
18
BLKING
18
30k 10k
Blanking pulse input. Set the V blanking pulse width to 300s or more. VILMAX = 0.8V VIHMIN = 2.8V
19 23 26
GND-B GND-G GND-R
0V
GNDs.
VCC VCC
0.5p
20 24 27
BOUT GOUT ROUT
620 20 24 27
R, G, and B signal outputs.
VCC 1k VCC
VCC
21 25 28
S/H-B S/H-G S/H-R
300 21 25 28 1k
Brightness sample-and-hold. Connect a capacitor to GND.
22
VCC
12V
12V power supply.
-5-
CXA2066S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC VCC 25k 50k 29 25k VCC VCC VCC
Description
29
ABL
ABL control input. Ground to GND when not using ABL.
VCC2 VCC2 100 VCC2
VCC2 15k
30
CSYNC
30
Sync on Green signal sync separator output (positive polarity). Typ.; High = 4.3V Low = 0.2V
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CXA2066S
I2C BUS Register Definitions Slave Address SLAVE RECEIVER; 40 (HEX) Register Table SUB ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH Sub Address 0000 V DET OFF CONTRAST (8) SHP OFF SYNC OFF VDET LEVEL 0 BLK MODE BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
CONTRAST BRIGHTNESS CUT OFF R CUT OFF G CUT OFF B OSD GAIN CUT OFF RGB SUB CONTRAST R SUB CONTRAST G SUB CONTRAST B T SW SHP GAIN
Controls the gain common to the R, G, and B channels. Since control is performed by multiplying with SUB CONTRAST, the white balance can be adjusted by SUB CONTRAST and the luminance can be adjusted by CONTRAST. 0: Gain minimum (-30dB or less) 255: Gain maximum (+17dB) Switches the blanking level. 0: Pedestal -0.6V 1: 0.5V fixed Controls the black level common for the R, G, and B channels. 0: Black level minimum (1V) 63: Black level maximum (3V) Controls Pin 3 (COF R) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) Controls Pin 4 (COF G) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) Controls Pin 5 (COF B) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V) -7-
Sub Address 0001
BLK MODE (1)
Sub Address 0001
BRIGHTNESS (6)
Sub Address 0010
CUT OFF R (8)
Sub Address 0011
CUT OFF G (8)
Sub Address 0100
CUT OFF B (8)
CXA2066S
Sub Address 0101
VDET LEVEL (2)
Controls the signal detection (VDET) slice level. 0: Slice level minimum (30mV when RIN = GIN = BIN) 3: Slice level maximum (220mV when RIN = GIN = BIN) Controls the OSD gain common to the R, G, and B channels. Since control is performed by multiplying with SUB CONTRAST (upper 6 bits), white balance and tracking for the video is obtained. 0: Gain minimum (0Vp-p) 63: Gain maximum (5Vp-p) Controls Pin 6 (COF RGB) output voltage. 0: Output voltage minimum (1V) 255: Output voltage maximum (4V)
Sub Address 0101
OSD GAIN (6)
Sub Address 0110
CUT OFF RGB (8)
Sub Address 0111
SUB CONTRAST R (8) Controls the R channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance. 0: Gain minimum (-30dB or less) 255: Gain maximum (+17dB) SUB CONTRAST G (8) Controls the G channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance. 0: Gain minimum (-30dB or less) 255: Gain maximum (+17dB) SUB CONTRAST B (8) Controls the B channel gain. Control is performed by multiplying with CONTRAST. Use for adjusting the white balance. 0: Gain minimum (-30dB or less) 255: Gain maximum (+17dB) VDET OFF (1) Controls the Pin 16 (VDET) output. 0: VDET output on 1: VDET output off Controls the sharpness function. 0: Sharpness on 1: Sharpness off Controls the Pin 30 (CSYNC) output. 0: SYNC output on 1: SYNC output off Controls the time constant during sharpness. 0: 50ns 1: 100ns Controls the sharpness gain. 0: Gain minimum (-30dB or less) 15: Gain maximum (+7dB) -8-
Sub Address 1000
Sub Address 1001
Sub Address 1010
Sub Address 1010
SHP OFF (1)
Sub Address 1010
SYNC OFF (1)
Sub Address 1010
T SW (1)
Sub Address 1010
SHP GAIN (4)
CXA2066S
Electrical Characteristics No. 1 Measurement item Symbol Current consumption ICC1 ICC2 Measurement contents VCC and VCC2 pins inflow current Input signal: None Input continuous 1MHz, 50MHz, and 100MHz sine waves at 0.7Vp-p. Measure the output amplitude gain difference at this time.
VOUT 50M Gain difference [dB] = 20 log VOUT 1M VOUT 100M Gain difference [dB] = 20 log VOUT 1M
Min. 65 30
Typ. 88 45
Max. 110 60
Unit mA mA
Frequency response (50MHz)
F4
-1.7
0
1.7
2
( (
) )
-5.5 -1.85 1.8
dB
RGB input signal (RGB input pins)
Frequency response (100MHz)
F5
0.7Vp-p CLP potential (approximately 1.7V) GND
Contrast control 1
Measure the level of the output signal amplitude VOUT when a 0.7Vp-p video signal is input. GCONT1 (ABL = 0V) VCONT1: Contrast = Sub Contrast = FF VCONT2: Contrast = 00/Sub Contrast = FF
Input signal
4.5
5.0
5.5
Vp-p
3
Contrast control 2
GCONT2
0.7Vp-p
-30
35
100
mVp-p
4
Sub Contrast control
Measure the level of the output signal amplitude VOUT when a 0.7Vp-p video signal is input. (Contrast = FF/Sub Contrast = 00/ ABL = 0V) GSUB
Input signal 0.7Vp-p
-30
35
100
mVp-p
-9-
CXA2066S
No.
Measurement item Symbol
Measurement contents Measure the OSD level of the output signal when an OSD pulse is input. GOSD1: OSD = 3F/Sub Contrast = FF GOSD2: OSD = 00/Sub Contrast = FF
RGB output signal OSD period
Min.
Typ.
Max.
Unit
GOSD1
4.4
5.0
5.6
Vp-p
5
OSD gain control
GOSD2
OSD level
-240
-70
80
mVp-p
VBRT1
Measure the black level of the RGB output signal. VBRT1: Brightness = 00 VBRT2: Brightness = 3F
RGB output signal
0.8
1.1
1.4
6
Brightness control
V
VBRT2
Black level GND
2.65
2.9
3.15
BLK control (BLK MODE = 0)
VBLK1
Measure the BLK level of the output signal when a BLK pulse is input.
400
560
720
7
BLK level (VBLK1)
mV
BLK control (BLK MODE = 1)
VBLK2
BLK level (VBLK2) GND
200
310
420
- 10 -
CXA2066S
No.
Measurement item Symbol Sharpness gain 1
Measurement contents Input a 30MHz sine wave to RGB at an amplitude of 0.1Vp-p, and measure the output level, and then calculate I/O gain. Gain difference [dB] = 20 log
Min.
Typ.
Max.
Unit
SHP1
8.9
10.9
12.9
(
Output level Input level
)
14.6 16.6 18.6 dB 9.2 11.2 13.2
Sharpness gain 2 8 Sharpness gain 3
SHP2
SHP3
(Contrast = 7F/Sub Contrast = FF/ ABL = 0V) SHP1: SHP GAIN = 0/T SW = 0 SHP2: SHP GAIN = F/T SW = 0 SHP3: SHP GAIN = 0/T SW = 1 SHP4: SHP GAIN = F/T SW = 0
Input signal
Sharpness gain 4
0.1Vp-p
SHP4
CLP potential (approximately 1.7V) GND
16.3
18.3
20.3
Input D range (VIN = 0.7V) 9 Input D range (VIN = 1.2V)
VIND1
VIND2
Measure the output level when 0.7Vp-p and 1.2Vp-p input video signals are input. (Contrast = CC, Sub Contrast = FF, Brightness = 00)
3.8
4.3
4.8 Vp-p
5.8
6.3
6.8
SYNCSEP SYNCHI output high level 10
Input a Sync on Green video signal to SYNCIN, and measure the CSYNC high level and low level.
4.1
4.4
4.7
V
High level
SYNCSEP output low level
SYNCLO
CSYNC GND Low level
100
200
300
mV
SYNCSEP output rise delay 11 SYNCSEP output fall delay
SDLYR
Input signal Vth = 50% Rise delay CSYNC Vth = 50%
42
50
ns
Fall delay
SDLYF
45
70
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CXA2066S
No.
Measurement item Symbol
Measurement contents
Min.
Typ.
Max.
Unit
VDET output high level 12 VDET output low level
VDETHI
Measure the VDET high level and low level when a 0.7Vp-p video signal is input to RGB.
4.1
4.4
4.7
V
VDETLO
VDET GND
High level Low level
200
280
400
mV
VDET output rise delay 13 VDET output fall delay
VDDLYR
Input signal Rise delay Vth = 50% 0.7Vp-p Fall delay
17
40
ns
VDET
Vth = 50%
VDDLYF
26
50
DAC output voltage (COFF = 00) 14 DAC output voltage (COFF = FF)
VCUT1 Measure the DAC output voltage (Pins 3, 4, 5, and 6) when COFF = 00/FF. VCUT2
0.9
1.1
1.3 V
3.8
4
4.2
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CXA2066S
I2C BUS Logic System No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Item High level input voltage Low level input voltage Low level output voltage SDA, during current inflow of 3mA Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transfer start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol VIH VIL VOL fSCL Min. 3.0 0 0 0 4.0 4.0 4.7 4.0 4.7 440 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 0.4 100 -- -- -- -- -- -- -- 1 300 -- Unit V V V kHz s s s s s ns ns s ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
- 13 -
CXA2066S
Electrical Characteristics Measurement Circuit
1 220 I2C BUS 2 220
SDA
CSYNC 30
SYNC SEP output
SCL
ABL 29
3
COF R
S/H-R 28
0.1F
4 DAC output 5
COF G
ROUT 27
R channel output
COF B
GND-R 26
6
COF RGB
S/H-G 25
0.1F
7 0.1F 75 47F 8 5V 0.1F 9 0.1F 75
RIN
GOUT 24
G channel output
VCC2
GND-G 23 47F
GIN
VCC 22 12V 0.1F 0.1F
10 SYNC IN 0.1F 75 11 BIN 0.1F 75 12 CLP
S/H-B 21
BOUT 20
B channel output
GND-B 19
13 OSD-R
BLKING 18
14 OSD-G
YS 17
15 OSD-B
VDET 16
Video detector output
- 14 -
CXA2066S
Electrical Characteristics Measurement Circuit (Frequency Response)
1 220 I2C BUS 2 220
SDA
CSYNC 30
SYNC SEP output
SCL
ABL 29
3
COF R
S/H-R 28
0.1F
4 DAC output 5
COF G
ROUT 27
R channel output
COF B
GND-R 26
6 1k 7 0.1F 50 47F 8 5V 0.1F 1k 0.1F 50 9
COF RGB
S/H-G 25
0.1F
RIN
GOUT 24
G channel output
VCC2
GND-G 23 47F
GIN
VCC 22 12V 0.1F 0.1F
10 SYNC IN 0.1F 1k 0.1F 50 12 CLP
S/H-B 21
11 BIN
BOUT 20
B channel output
GND-B 19
13 OSD-R
BLKING 18
14 OSD-G
YS 17
15 OSD-B
VDET 16
Video detector output
- 15 -
CXA2066S
Description of Operation 1. Sharpness function The RGB signals input to Pins 7, 9, and 11 are mixed at a ratio of 0.6G + 0.3R + 0.1B to form the Y signal. The high-frequency component is removed from this Y signal by a differentiation circuit, and the amplitude is controlled by a gain control circuit. The signal which undergoes gain control (sharpness component) has its amplitude clipped by a limiter circuit and is then added to the R, G, and B signals.
SHP GAIN = 0 (HEX) or SHP OFF = 1
No sharpness component
100%
Section not sent to RGB output because of the limiter Limiter level = 30% (Typ.)
SHP GAIN = F (HEX) 50ns (T SW = 0) 100ns (T SW = 1) 10% RGB output when RIN = GIN = BIN = 0.7Vp-p The output level is set to 100%.
100%
2. VBLK synchronous DAC refresh system The VBLK signal is removed from the composite BLK signal which has been input to Pin 18, and the data for each control DAC is overwritten all at once in synchronization with this VBLK signal. The received I2C bus data is held by a latch until the next VBLK signal arrives. As a result, I2C bus data transmission from the microcomputer is timing-free. Set the V blanking pulse width which is input to Pin 18 at 300s or more.
- 16 -
VBLK Synchronous DAC Refresh System
Vsync
Bus data transmission Data group (2)
Transmission period Data group (3)
Data group (1)
enable
DAC refresh enable signal
- 17 -
disable
DAC refresh signal
The newest transmission data before Vsync is written to the DAC. In this case, the data in (1) is written.
The DAC is not overwritten while the bus data in the Vsync period is being transmitted. The transmitted data is held.
Overwritten by the data in (3). If (3) is not transmitted, this is overwritten by the data in (2).
CXA2066S
CXA2066S
Application Circuit
1 220 I2C BUS 2 220
SDA
CSYNC 30
SYNC SEP output
SCL
ABL 29
ABL input
3
COF R
S/H-R 28 0.1F
4 DAC output 5
COF G
ROUT 27
R channel output
COF B
GND-R 26
6
COF RGB
S/H-G 25 0.1F
R channel input 0.1F 75 5V 0.1F G channel input 0.1F 75 Sync on Green input 0.1F 75 B channel input 0.1F 75 Clamp pulse input 47F
7
RIN
GOUT 24
G channel output
8
VCC2
GND-G 23 47F
9
GIN
VCC 22 0.1F
12V
10 SYNC IN
S/H-B 21 0.1F
11 BIN
BOUT 20
B channel output
12 CLP
GND-B 19 Blanking pulse input VBLK 300s
OSD pulse (R channel) input
13 OSD-R
BLKING 18
OSD pulse (G channel) input
14 OSD-G
YS 17
YS input
OSD pulse (B channel) input
15 OSD-B
VDET 16
Video detector output
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 18 -
CXA2066S
Example of Representative Characteristics
CONTRAST Control Characteristics
5 SUB CONTRAST = 255 SUB CONTRAST = 127 Output amplitude [Vp-p] Video IN = 0.7Vp-p 3 OSD output amplitude [Vp-p] 4 4 5 SUB CONTRAST = 255 SUB CONTRAST = 127
OSD Gain Control Characteristics
3
2
2
1
1
0
0
50
100 150 CONTRAST DATA
200
250
0
0
50
100 150 OSD GAIN DATA
200
250
SUBCONT Control Characteristics
5 CONTRAST = 255 CONTRAST = 127 4 Output amplitude [Vp-p] Output amplitude [Vp-p] Video IN = 0.7Vp-p 3 4 5
ABL Control Characteristics
Video IN = 0.7Vp-p SUB CONTRAST = FF (HEX) CONTRAST = FF (HEX)
3
2
2
1
1
0
0
50
100 150 200 SUB CONTRAST DATA
250
0
0
1 2 3 4 Voltage Applied to Pin 29 [V]
5
- 19 -
CXA2066S
Notes on Operation 1. Set the output for ROUT, GOUT, and BOUT for reception at high impedance. 2. Make the wiring from ROUT, GOUT, and BOUT to the power amplifier as short as possible. 3. Connect the VCC and VCC2 decoupling capacitor so that the ceramic capacitor and electrolytic capacitor are connected in parallel and the distance from the IC is as short as possible. 4. Connect the clamp capacitor for RIN, GIN, BIN, S/H-R, S/H-G, S/H-B so that the distance from the IC is as short as possible. 5. Set the output to OFF when the VDET output is not used (Set I2C BUS VDETOFF "1").
- 20 -
CXA2066S
Package Outline
Unit: mm
30PIN SDIP (PLASTIC)
+ 0.4 26.9 - 0.1
30
16
+ 0.3 8.5 - 0.1
+ 0.1 .05 0.25 - 0
1 1.778
15
0.5 MIN
+ 0.4 3.7 - 0.1
10.16
0 to 15
Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type.
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-30P-01 SDIP030-P-0400 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 1.8g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
- 21 -
3.0 MIN

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